1. Field of the Invention
The invention relates to packaging technology and more particularly packaging technology in the context of improving integrated circuit device performance.
2. Background
Computer systems typically include modules that communicate with a processor using a bus. One example of such a module is a memory module containing one or more integrated circuit memories. The bus is basically a transmission line that carries signals such as clock, time, data, control, and address signals between the processor, modules, and other bus devices. A popular type of integrated circuit memory is dynamic random access memory (DRAM). A typical configuration involves coupling a plurality of integrated circuit memories each comprising for example, 64 megabyte (Mb)/72 Mb, 128 Mb/144 Mb to 256 Mb and 352 Mb DRAM circuits on a memory module. The memory module is suitable for connection to a printed circuit board (PCB) such as a mother board containing an application specific integrated circuit (ASIC). In this context, a memory module may be suitable for use in a broad range of applications, including, but not limited to, computer memory, personal computers, and work stations.
The RIMM™ memory module designed by Rambus Inc. of Mountain View, Calif. consists of 128 Mb/144 Mb DRAM dies organized as eight (8) Mega words by 16 or 18 bits. Such technology permits 600 Megahertz (MHz), 711 MHz, or 800 MHz transfer rates using conventional system and board design technologies. The modules are capable of sustained data transfers at 1.25 nanoseconds (ns) per two (2) bytes. The individual DRAM dies (RDRAM™ dies) are arranged in packages on the module and, in the case of multiple DRAM die packages, serially connected to an adjacent package.
Packaging technology of memory devices (e.g., DRAM memory devices) is typically described as one tape layer packaging. In a general sense, an integrated circuit contains a plurality of bond pads to address the various devices on the circuit (e.g., the various DRAM cells). Through packaging technology, the individual bond pads of an integrated circuit are coupled to corresponding bond pads, typically having a greater pitch, on a package. The bond pad pitch is then suitable for coupling to the module. The package thus acts as a transformer between the mechanical pitch of the integrated circuit and the mechanical pitch of the module. The package generally utilizes a single metal layer to transform the routing pitch between the die and package so that the pitch of the package corresponds to the module. The single metal layer routes to contact structures on the surface of the package, such as ball grid arrays (BGAs), suitable for coupling to the module. Bonding configurations between the integrated circuit and the module are typically classified as center-bonded where the die connections are in the center of the die and edge-bonded connections where the die connections are on the edge of the die.
Memory module manufacturers or designers may use the electrical parameters of the package (e.g., the parasitics of the package including the integrated circuit chip or die) as part of the electrical design of the module. Performance evaluations of such designs are used to characterize and classify the capabilities (e.g., frequency capabilities) of the module. As the signal frequency is continually increased to speeds of 800 megatransfer or greater, the contribution of the package parasitics plays a larger role. For example, for a given transmission line, DRAM packages have a resistance, an inductance, and a capacitance. In performance simulations, these electrical parameters are generally considered ideal. However, factors such as the capacitance of a package trace attributable to die activity or signal patterns and trace to trace coupling can be significant in, for example, effecting the impedance and propagation velocity of a signal. Impedance to propagation velocity impact the timing margin of the signal as well as the voltage margin. Similarly, the inductance, due to, for example, inductive package trace coupling, may affect signal integrity, particularly affecting voltage margins. Thus, what is needed is an improved package and module configuration that minimizes die and package parasitics.